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d a t a sh eet product speci?cation file under integrated circuits, ic22 1995 oct 18 integrated circuits saa7110; saa7110a one chip front-end 1 (ocf1)
1995 oct 18 2 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 system view 7 block diagram 8 pinning 9 functional description 9.1 analog input processing (see fig.5) 9.2 analog control circuits 9.3 chrominance processing (see fig.6) 9.4 luminance processing (see fig.7) 9.5 yuv-bus (digital outputs) 9.6 synchronization (see fig.7) 9.7 clock generation circuit 9.8 power-on reset 9.9 rtco output 10 gain charts 11 limiting values 12 characteristics 13 timing 14 output formats 15 clock system 15.1 clock generation circuit 15.2 power-on control 16 i 2 c-bus description 16.1 i 2 c-bus format 16.2 i 2 c-bus receiver/transmitter tables 16.3 i 2 c-bus detail 16.4 i 2 c-bus detail (continued) 17 source selection management 18 anti-alias filter graphs 19 coring function 19.1 coring function adjustment by subaddress 06h to affect band filter output adjustment 20 luminance filter graphs 21 i 2 c-bus start set-up 21.1 remarks to table 66 22 application information 23 start-up, source select and standard detection flow example 23.1 code 0 startup and standard procedure 23.2 mode 0 source select procedure 23.3 mode 1 source select procedure 23.4 mode 2 source select procedure 23.5 mode 3 source select procedure 23.6 mode 4 source select procedure 23.7 mode 5 source select procedure 23.8 mode 6 source select procedure 23.9 mode 7 source select procedure 23.10 mode 8 source select procedure 24 package outline 25 soldering 25.1 introduction 25.2 reflow soldering 25.3 wave soldering 25.4 repairing soldered joints 26 definitions 27 life support applications 28 purchase of philips i 2 c components
1995 oct 18 3 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 1 features six analog inputs (6 cvbs or 3 y/c or combinations) three analog processing channels three built-in analog anti-aliasing filters analog signal adding of two channels two 8-bit video cmos analog-to-digital converters fully programmable static gain for the main channels or automatic gain control for the selected cvbs/y channel selectable white peak control signal luminance and chrominance signal processing for pal b/g, ntsc m and secam full range hue control automatic detection of 50/60 hz field frequency, and automatic switching between standards pal and ntsc, secam forceable horizontal and vertical sync detection for all standards cross-colour reduction by chrominance comb filtering for ntsc or special cross-colour cancellation for secam uv signal delay lines for pal to correct chrominance phase errors the yuv-bus supports a data rate of: C 780 f h = 12.2727 mhz for 60 hz (ntsc) C 944 f h = 14.75 mhz for 50 hz (pal/secam) square pixel format with 768/640 active samples per line on the yuv-bus ccir 601 level compatible 4:2:2 and 4:1:1 yuv output formats in 8-bit resolution user programmable luminance peaking for aperture correction compatible with memory-based features (line-locked clock, square pixel) requires only one crystal (26.8 mhz) for all standards real time status information output (rtco) brightness contrast saturation (bcs) control for the yuv-bus negation of picture possible one user programmable general purpose switch on an output pin switchable between on-chip clock generation circuit (cgc) and external cgc (saa7197) power-on control i 2 c-bus controlled. 2 applications desktop video multimedia digital television image processing video phone video picture grabbing. 3 general description the one chip front-end saa7110; saa7110a is a digital multistandard colour decoder (ocf1) on the basis of the dig-tv2 system with two integrated analog-to-digital converters (adcs), a clock generation circuit (cgc) and brightness contrast saturation (bcs) control. the cmos circuit saa7110; saa7110a, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. the decoder is based on the principle of line-locked clock decoding. it operates square-pixel frequencies to achieve correct aspect ratio. monitor controls are provided to ensure best display. the circuit is i 2 c-bus controlled. 4 quick reference data symbol parameter min. max. unit v dda analog supply voltage 4.75 5.25 v v ddd digital supply voltage 4.5 5.5 v t amb operating ambient temperature 0 70 c
1995 oct 18 4 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 5 ordering information 6 system view type number package name description version saa7110 plcc68 plastic leaded chip carrier; 68 leads sot188-2 saa7110a plcc68 plastic leaded chip carrier; 68 leads sot188-2 fig.1 system diagram. handbook, full pagewidth video memory controller vmc one chip front-end ocf1 video frame memory six video inputs pc isa - bus yuv - bus i 2 c clock mgc821
1995 oct 18 5 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 7 block diagram handbook, full pagewidth fein (muxc) xtalo xtali reset y7 to y0 scl sda sa gpsw (vblk) ap sp hs rtco hsy hcl vs saa7110 saa7110a y y ad2 ad3 analog control test control block analog processing con bypass 41 38 37 36 30 66 65 42 63 64 8 6 5 4 31 29 32 llc2 cref uv7 to uv0 i.c. 7, 8, 9 ai42 ai41 ai32 ai31 ai22 ai21 11 13 15 17 19 21 39 mgc820 40 odd (vl) plin (hl) cgce lfco llc v ssa0 v dda0 25 24 68, 52, 44, 34, 27 67, 51, 43, 35, 28 v ssa2 to v ssa4 v dda2 to v dda4 v ss v dd v ss(s) 18, 14, 10 20, 16, 12 22 y/cvbs c/cvbs 1 2 3 26 33 aout 23 href chrominance circuit luminance circuit synchronization circuit clock generation circuit brightness contrast saturation control and output formatter power-on control uv y 55 to 62 45 to 50, 53, 54 i 2 c-bus interface i 2 c-bus control clocks fig.2 block diagram.
1995 oct 18 6 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 8 pinning symbol pin description sp 1 test pin input; (shift pin) connect to ground for normal operation ap 2 test pin input; (action pin) connect to ground for normal operation rtco 3 real time control output. this pin is used to ?t serially the increments of the hpll and fsc-pll and information of the pal or secam sequence. sa 4 i 2 c-bus slave address select input. low: slave address = 9ch for write, 9dh for read; high = 9dh for write, 9fh for read. sda 5 i 2 c-bus serial data input/output scl 6 i 2 c-bus serial clock input i.c. 7 reserved pin; do not connect i.c. 8 reserved pin; do not connect i.c. 9 reserved pin; do not connect v ssa4 10 ground for analog input 4 ai42 11 analog input 42 v dda4 12 supply voltage (+5 v) for analog input 4 ai41 13 analog input 41 v ssa3 14 ground for analog input 3 ai32 15 analog input 32 v dda3 16 supply voltage (+5 v) for analog input 3 ai31 17 analog input 31 v ssa2 18 ground for analog input 2 ai22 19 analog input 22 v dda2 20 supply voltage (+5 v) for analog input 2 ai21 21 analog input 21 v ss(s) 22 substrate ground aout 23 analog test output; do not connect v dda0 24 supply voltage (+5 v) for internal cgc (clock generation circuit) v ssa0 25 ground for internal cgc lfco 26 line frequency control output; this is the analog clock control signal driving the external cgc. the frequency is a multiple of the actual line frequency (nominally 7.375/6.13636 mhz). the signal has a triangular form with 4-bit accuracy. v dd 27 supply voltage (+5 v) v ss 28 ground llc 29 line-locked clock input/output (cgce = 1, output; cgce = 0, input). this is the system clock, its frequency is 1888 f h for 50 hz/625 lines per ?eld systems and 1560 f h for 60 hz/525 lines per ?eld systems; or variable input clock up to 32 mhz in input mode. llc2 30 line-locked clock 1 2 output; f llc2 = 0.5 f llc (cgce = 1, output; cgce = 0, high impedance). cref 31 clock reference input/output (cgce = 1, output; cgce = 0, input). this is a clock quali?er signal distributed by the internal or an external clock generator circuit (cgc). using cref all interfaces on the yuv-bus are able to generate a bus timing with identical phase.
1995 oct 18 7 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a reset 32 reset active low input/output (cgce = 1, output; cgce = 0, input); sets the device into a de?ned state. all data outputs are in high impedance state. the i 2 c-bus is reset (waiting for start condition). using the external cgc, the low period must be maintained for at least 30 llc clock cycles. cgce 33 cgc enable active high input (cgce = 1, on-chip cgc active; cgce = 0, external cgc mode, use saa7197). v dd 34 supply voltage (+5 v) v ss 35 ground hcl 36 horizontal clamping input/output pulse (programmable via i 2 c-bus bit pulio: pulio = 1, output; pulio = 0, input). this signal is used to indicate the black level clamping period for the analog input interface. the beginning and end of its high period (only in the output mode) can be programmed via the i 2 c-bus registers 03h, 04h in 50 hz mode and registers 16h, 17h in 60 hz mode, active high. hsy 37 horizontal synchronization input/output indicator (programmable via i 2 c-bus bit pulio: pulio = 1, output; pulio = 0, input). this signal is fed to the analog interface. the beginning and end of its high period (only in the output mode) can be programmed via the i 2 c-bus registers 01h, 02h in 50 hz mode and registers 14h, 15h in 60 hz mode, active high. hs 38 horizontal synchronization output (programmable; the high period is 128 llc clock cycles). the position of the positive slope is programmable in 8 llc increments over a complete line (64 m s) via the i 2 c-bus register 05h in 50 hz mode or register 18h in 60 hz mode. plin (hl) 39 pal identi?er not output; marks for demodulated pal signals the inverted line (plin = low) and a non-inverted line (plin = high) and for demodulated secam the dr line (plin = low) and the db line (plin = high). select plin function via i 2 c-bus bit rtse = 0. (h-pll locked output; a high state indicates that the internal pll has locked. select hl function via i 2 c-bus bit rtse = 1). odd (vl) 40 odd/even ?eld identi?cation output; a high state indicates the odd ?eld. select odd function via i 2 c-bus bit rtse = 0. (vertical locked output; a high state indicates that the internal vertical noise limiter (vnl) is in a locked state. select vl function via i 2 c-bus bit rtse = 1). vs 41 vertical synchronization input/output (programmable via i 2 c-bus bit oehv: oehv = 1, output; oehv = 0, input). this signal indicates the vertical synchronization with respect to the yuv output. the high period of this signal is approximately six lines if the vnl function is active. the positive slope contains the phase information for a de?ection controller, for example the tda9150. in input mode this signal is used to synchronize the vertical gain and clamp blanking stage, active high. href 42 horizontal reference output; this signal is used to indicate data on the digital yuv-bus. the positive slope marks the beginning of a new active line. the high period of href is either 768 y samples or 640 y samples long depending on the detected ?eld frequency (50/60 hz mode). href is used to synchronize data multiplexer/demultiplexers. href is also present during the vertical blanking interval. v ss 43 ground v dd 44 supply voltage (+5 v) symbol pin description
1995 oct 18 8 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a y7 45 upper 6 bits of the 8-bit luminance (y) digital output. as part of the digital yuv-bus (data rate llc/2), or a/d2(3) output (data rate llc/2) selectable via i 2 c-bus bit sqpb = 1. y6 46 y5 47 y4 48 y3 49 y2 50 v ss 51 ground v dd 52 supply voltage (+5 v) y1 53 lower 2 bits of the 8-bit luminance (y) digital output. as part of the digital yuv-bus (data rate llc/2), or a/d2(3) output (data rate llc/2) selectable via i 2 c-bus bit sqpb = 1. y0 54 uv7 55 8-bit digital uv (colour difference) output; multiplexed colour difference signal for u and v component of demodulated cvbs or chrominance signal. the format and multiplexing scheme can be selected via i 2 c-bus control. these signals are part of the digital yuv-bus (data rate llc/2), or a/d3(2) output (data rate llc/2) selectable via i 2 c-bus bit sqpb = 1. uv6 56 uv5 57 uv4 58 uv3 59 uv2 60 uv1 61 uv0 62 fein (muxc) 63 fast enable input (active low); this signal is used to control fast switching on the digital yuv-bus. a high at this input forces the ic to set its y and uv outputs to the high impedance state. to use this function set i 2 c-bus bits ms24 and ms34 and muyc to low. (multiplex components input; control signal for the analog multiplexers for fast switching between locked y/c signals or locked cvbs signals. fein automatically ?xed to low (digital yuv-bus enabled), if one of the three muxc functions are selected (ms24 or ms34 or muyc = high). gpsw (vblk) 64 general purpose switch output; the state of this signal is programmable via i 2 c-bus register 0dh, bit 1. select gpsw function via i 2 c-bus bit vblka = 0. (vertical blank test output; select vblk via i 2 c-bus bit vblka = 1). xtalo 65 crystal oscillator output (to 26.8 mhz crystal); not used if ttl clock is used. xtali 66 crystal oscillator input (from 26.8 mhz crystal) or connection of external oscillator with ttl compatible square wave clock signal. v ss 67 ground v dd 68 supply voltage (+5 v) symbol pin description
1995 oct 18 9 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.3 pin configuration. handbook, full pagewidth saa7110 saa7110a mgc822 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 y7 y6 y5 y4 y3 y2 y1 y0 uv7 uv6 uv5 uv4 uv3 uv2 44 27 28 29 llc llc2 cref reset cgce hs vs plin (hl) odd (vl) href hcl hsy 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 xtali xtalo sp ap rtco sa i.c. i.c. i.c. sda scl gpsw (vblk) fein (muxc) uv0 uv1 65 64 63 62 61 v ssa4 ai42 v dda4 ai41 ai32 ai31 ai22 ai21 aout v ssa3 v dd v ss v dda3 v ssa2 v dda2 v ss(s) v dda0 v dd v ss v dd v ss v ss v dd v ss v dd v ssa0 lfco
1995 oct 18 10 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 9 functional description 9.1 analog input processing (see fig.5) the saa7110; saa7110a offers six analog signal inputs, two analog main channels with clamping circuit, analog amplifier, anti-alias filter and video cmos adc. a third analog channel also with clamping circuit, analog amplifier and anti-alias filter can be added or switched to both main channels directly before the adcs. 9.2 analog control circuits the clamping control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and filter the clamping voltage. the normal digital clamping level for luminance or cvbs signals is 64 and for chrominance signals is128. the gain control circuits generate via i 2 c-bus the static gain levels for the three analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (agc). the agc is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the anti-alias filters are adapted to the clock frequency. the vertical blanking control circuit generates an i 2 c-bus programmable vertical blanking pulse. during the vertical blanking time gain and clamping control are frozen. the fast switch control circuit is used for special applications. 9.2.1 c lamping the coupling capacitor is used as clamp capacitance for each input. an internal digital clamp comparator generates the information concerning clamp-up or clamp-down. the clamping levels for the two adc channels are adjustable over the 8-bit range (1 to 254). clamping time in normal use is set with the hcl pulse at the back porch of the video signal. the clamping pulse hcl is user adjustable. 9.2.2 g ain control (see fig.4) the luminance agc can be used for every channel were luminance or cvbs is being received. agc active time is the sync tip of the video signal. the sync tip pulse hsy is user adjustable. the agc can be switched off and the gain for the three main input channels can be adjusted independently. signal (white) peak control limits the gain at signal overshoots. the flow charts (see figs 8 and 9) show more details of the agc. the influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. 9.3 chrominance processing (see fig.6) the 8-bit chrominance signal passes the input interface, the chrominance bandpass filter to eliminate dc components, and is finally fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator dto1 with 90 degrees phase shift are applied. the frequency is dependent on the present colour standard. the multiplier operates as a quadrature demodulator for all pal and ntsc signals; it operates as a frequency down mixer for secam signals. the two multiplier output signals are converted to a serial uv data stream and applied to two low-pass filter stages, then to a gain controlled amplifier. a final multiplexed low-pass filter achieves, together with the preceding stages, the required bandwidth performance. the pal and ntsc originated signals are applied to a comb filter. the signal originated from secam is fed through a cloche filter (0 hz centre frequency), a phase demodulator and a differentiator to obtain frequency demodulated colour difference signals. the secam signal is fed after de-emphasis to a cross-over switch, to provide both the serial transmitted colour difference signals. these signals are fed to the bcs control and finally to the output fomatter stage and to the output interface. fig.4 automatic gain control range. handbook, halfpage analog input level controlled adc input level maximum minimum range 8.8 db 0 db 0 db mgc823 + 2.8 db - 6 db
1995 oct 18 11 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 9.4 luminance processing (see fig.7) the 8-bit luminance signal, a digital cvbs format or a luminance format (s-vhs, hi8), is fed through a switchable prefilter. high frequency components are emphasized to compensate for loss. the following chrominance trap filter (f c = 4.43 or 3.58 mhz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for s-video (s-vhs, hi8) signals. the high frequency components of the luminance signal can be peaked (control for sharpness improvement via i 2 c-bus) in two bandpass filters with selectable transfer characteristics. a coring circuit with selectable characteristics improves the signal once more. this signal is then added to the original (unpeaked) signal. a switchable amplifier achieves common dc amplification, because the dc gains are different in both chrominance trap modes. the improved luminance signal is fed via the variable delay to the bcs control and the output interface. 9.5 yuv-bus (digital outputs) the 16-bit yuv-bus transfers digital data from the output interfaces to a feature box, or a field memory, a digital colour space converter (saa 7192 dcsc) or a video enhancement and digital-to-analog processor (saa7165 veda2). the outputs are controlled by an output enable chain ( fein on pin 63). the yuv data rate equals llc2. timing is achieved by marking each second positive rising edge of the clock llc in conjunction with cref (clock reference). the output signals y7 to y0 are the bits of the digital luminance signal. the output signals uv7 to uv0 are the bits of multiplexed colour difference signals (b - y) and (r - y). the frame in the format tables is the time, required to transfer a full set of samples. in the event of 4 :2:2 format two luminance samples are transmitted in comparison to one u and one v sample within the frame. the time frames are controlled by the href signal. fast enable is achieved by setting input fein to low. the signal is used to control fast switching on the digital yuv-bus. high on this pin forces the y and uv outputs to a high-impedance state. 9.6 synchronization (see fig.7) the pre-filtered luminance signal is fed to the synchronization stage. it's bandwidth is reduced to 1 mhz in a low-pass filter. the synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop filter to accumulate all phase deviations. adjustable output signals hcl and hsy are generated in accordance with analog front end requirements. the output signals hs, vs, and plin are locked to the timing reference, guaranteed between the input signal and the href signal, as further improvements to the circuit may change the total processing delay. it is therefore not recommended to use them for applications which require absolute timing accuracy to the input signals. the loop filter signal drives an oscillator to generate the line frequency control signal lfco. 9.7 clock generation circuit the internal cgc generates all clock signals required for the one chip front-end. the output signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency (7.38 mhz = 472 f h in 50 hz systems and 6.14 mhz = 360 f h in 60 hz systems). internally the lfco signal is multiplied by a factor of 2 or 4 in the pll circuit (including phase detector, loop filtering, vco and frequency divider) to obtain the llc and llc2 output clock signals. the rectangular output clocks have a 50% duty factor. it is also possible to operate the ocf1 with an external cgc (saa7197) providing the signals llc and cref. the selection of the internal/external cgc will be controlled by the cgce input signal. 9.8 power-on reset power-on reset is activated at power-on (using only internal cgc), when the supply voltage decreases below 3.5 v. the indicator output reset is low for a time. the reset signal can be applied to reset other circuits of the digital tv system. 9.9 rtco output the real time control and status output signal contains serial information about actual system clock, subcarrier frequency and pal/secam sequence. the signal can be used for various applications in external circuits, for example, in a digital encoder to achieve clean encoding.
1995 oct 18 12 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth analog control mgc824 source switch clamp circuit analog amplifier analog amplifier analog amplifier gain control clamp control cross multiplexer anti-alias filter bypass switch source switch clamp circuit anti-alias filter bypass switch fast switch adder fast switch adder fast switch control vertical blanking control source switch clamp circuit anti-alias filter anti-alias control bypass switch test selector fuse fuse fuse refs4 ains4 aind4 refs3 refs2 ains3 aind3 ains2 aind2 clts cls2 cls3 cls4 aosl adc adc ysel csel two2 two3 v dda2 to v dda4 v ssa2 to v ssa4 ai42 ai41 ai32 ai31 ai22 ai21 i.c. i.c. i.c. v ss(s) 11 20, 16, 12 18, 14, 10 13 15 17 19 21 9 8 7 22 cll2n cll3n wipa glim hold wipe sbot gasl gaco gai2 gai3 gai4 iwip igai vbps vbpr vbco muyc ms24 ms34 mx24 mx34 mud1 mud2 wisl ival wval gudl wirs gas2 gas3 gad2 gad3 wrse 23 aout fig.5 analog input processing and analog control part.
1995 oct 18 13 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth input interface chrominance bandpass output formatter and interface quadrature demodulator low-pass low-pass gain control cloch filter loopfilter pi2 loop filter pi1 sequence processor phase demodulator amplitude detector brightness contrast saturation control comb filters and secam recombination burst gate accumulator discrete time oscillator (dto1) and divider standard control brig cont satn differentiator de-emphasis sxcr code byps chrs colo secs chcv cktq ckts lfis seqa sese plse altd v dd v ss chrominance circuit 68, 52, 44, 34, 27 67, 51, 43, 35, 28 63 42 ofts chsb oeyc oehv sqpb hrmv hrfs seqa huec fein (muxc) href uv7 to uv0 y7 to y0 45 to 50, 53, 54 mgc825 55 to 62 fig.6 multi-standard decoder part.
1995 oct 18 14 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth prefilter prefilter sync i 2 c-bus interface i 2 c-bus control sync slicer test control block chrominance trap phase detector fine phase detector coarse loop filter 2 delay adjustment line-locked clock generator discrete time oscillator (dto2) crystal clock generator variable bandpass filter coring weighting and adding stage variable delay power-on control pref byps cori aper ydel clock(3 to 0) bfby pref bpss matching amplifier dac6 clock generation circuit dac4 counter vertical processor fidt hlck sttc vblka sstb gpsw vnoi fsei aufd hs6b hs6s hc6b hc6s pulio oehv scen idel hsyb hsys hclb hcls hphi hp6i synchronization circuit luminance circuit hlck vtrc hpll hlck ap sp sa scl sda 36 64 456 41 37 38 39 40 25 24 33 3 hcl hs vs cgce odd (vl) v ssa0 v dda0 rtco hsy plin (hl) 26 65 66 30 29 31 32 reset cref llc llc2 xtali xtalo lfco gpsw (vblk) 2 1 mgc826 fig.7 luminance and synchronization part.
1995 oct 18 15 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 10 gain charts fig.8 clamp and gain flow chart. clau = clamp up. vblk = vertical blanking pulse. wipe = white peak level (adjustable). sbot = sync bottom level (adjustable). cll = clamp level (adjustable). claa = clamp active. hsy = horizontal sync pulse. hcl = horizontal clamp pulse. handbook, full pagewidth adc analog in vblk no blanking active claa = 1 hcl < ccl hsy > sbot > wipe claa = 0 clau = 1 clau = 0 10 10 mgc827 + clamp - clamp + gain - gain - gain slow + gain no clamp 10 10 10 10 <- clamp gain ->
1995 oct 18 16 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a handbook, full pagewidth analog input amplifier anti-alias amplifier adc8 decoder input x hsy wrse > wipe > wipe < sbot < sbot wirs x = 1 x = 0 - ival + ival - wval + / - 0 + 4/f + 4/l gain accumulator (20 bits) actual gain value 8-bit (agv) [ - 3/ + 6 db] x stop hsy y update fgv mgc828 agv gain value 8-bit 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 vblk 1 0 no action msb 6 lsb 2 *iwip *igai *iwip fig.9 luminance agc flow chart. x = system variable (start with logic 0). y = iagv-fgvi > gudl. vblk = vertical blanking pulse. hsy = horizontal sync pulse. sbot = sync bottom level (adjustable). wipe = white peak level (adjustable). ival = integration value gain (adjustable). wval = integration value wipe (adjustable). igai = integration factor gain (adjustable). iwip = integration factor wipe (adjustable). agv = actual gain value. fgv = frozen gain value. gudl = gain update level (adjustable). wrse = white peak reset enable. wirs = white peak reset select. l = line. f = field.
1995 oct 18 17 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 11 limiting values in accordance with the absolute maximum rating system (iec 134); all ground pins and all supply pins connected together. note 1. compare with typical total power consumption in chapter characteristics. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 12 characteristics v ddd =5v; v dda =5v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dda analog supply voltage - 0.5 +7.0 v v ddd digital supply voltage - 0.5 +7.0 v v i(a) analog input voltage - 0.5 +7.0 v v i(d) digital input voltage - 0.5 +7.0 v v diff voltage difference between v ssaall and v ssall - 100 mv t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c t amb(bias) operating ambient temperature under bias - 10 +80 c p tot total power dissipation v dda =v ddd = 7 v; note 1 - 2.5 w v esd electrostatic discharge all pins note 2 - 2000 +2000 v symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage 4.75 5.0 5.25 v v ddd digital supply voltage 4.5 5.0 5.5 v i dda(tot) total analog supply current -- 150 ma i ddd(tot) total digital supply current -- 250 ma p tot total power dissipation - 1.2 1.7 w analog part i clamp clamping current v i = 1.25 v dc - 2 - +2 m a v i(p-p) input voltage (peak-to-peak value), ac coupling required c couple = 10 nf 0.5 1.0 1.38 v ? z i ? input impedance clamping current off 200 -- k w c i input capacitance -- 10 pf a ct channel crosstalk f i < 5 mhz -- 50 - db analog-to-digital converters b analog bandwidth at - 3db - 15 - mhz f diff differential phase ampli?er + aaf = bypass - 2 - deg g diff differential gain ampli?er + aaf = bypass - 2 - % f llc adc clock rate 11 - 16 mhz dle dc differential linearity error - 1 2 - lsb ile dc integral linearity error - 1 - lsb
1995 oct 18 18 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a digital inputs v il low level input voltage sda and scl - 0.5 - +1.5 v v ih high level input voltage sda and scl 3.0 - v dd + 0.5 v v il(clk) low level input voltage for clocks - 0.5 - +0.6 v v ih(clk) high level input voltage for clocks 2.4 - v dd + 0.5 v v ih(xtali) high level input voltage xtali 3.0 - v dd + 0.5 v v il(n) low level input voltage all other inputs - 0.5 - +0.8 v v ih(n) high level input voltage all other inputs 2.0 - v dd + 0.5 v i li input leakage current -- 10 m a c i(clk) input capacitance for clocks -- 10 pf c i(i/o) input capacitance i/os at high impedance -- 8pf c i(n) input capacitance all other inputs -- 8pf digital outputs v lfco lfco output voltage (peak-to-peak value) note 1 1.4 - 2.6 v v ol low level output voltage note 2 0 - 0.6 v v oh high level output voltage note 2 2.4 - v dd v v ol(clk) low level output voltage for clocks - 0.5 - +0.6 v v oh(clk) high level output voltage for clocks 2.6 - v dd + 0.5 v clock input timing (llc) t cy cycle time 31 - 45 ns d duty factor for t llch /t cy 40 - 60 % t r rise time v i = 0.6 to 2.4 v -- 5ns t f fall time v i = 2.4 to 0.6 v -- 5ns control and cref input timing (note 3) t su;dat input data set-up time 11 -- ns t hd;dat input data hold time 3 -- ns t hd;fein input data hold time for fein 3 -- ns t hd;other input data hold time all other inputs note 3 6 -- ns symbol parameter conditions min. typ. max. unit
1995 oct 18 19 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a data and control output timing (note 4) c l(data) output load capacitance (data, href and vs) 15 - 50 pf c l(control) output load capacitance (control) 7.5 - 25 pf t hd;dat output data hold time c l =15pf 13 -- ns t pd(data) propagation delay from negative edge of llc (data, href and vs) c l =50pf -- 29 ns t pd(control) propagation delay from negative edge of llc (control) c l =25pf -- 29 ns t pd(z)) propagation delay from negative edge of llc (to 3-state) note 5 -- 15 ns clock output timing (llc and llc2) c l(llc) output load capacitance 15 - 40 pf t cy cycle time llc 31.5 - 45 ns llc2 63 - 90 ns d duty factors for t llch /t llc and t llc2h /t llc2 40 - 60 % t r rise time 0.6 to 2.6 v -- 5ns t f fall time 2.6 to 0.6 v -- 5ns t d delay time llc output to llc2 output v i = 1.5 v; c llc/llc2 = 40 pf; note 6 -- 8ns data quali?er output timing (cref) t hd;cref output hold time c l =15pf 4 -- ns t pd;cref propagation delay from positive edge of llc c l =40pf -- 20 ns horizontal pll f hnom nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f h /f hnom permissible static deviation 50 hz ?eld -- 5.6 % 60 hz ?eld -- 6.7 % subcarrier pll f hnom nominal subcarrier frequency pal - 4433618 - hz ntsc - 3579545 - hz d f h /f hnom lock-in range 400 -- hz symbol parameter conditions min. typ. max. unit
1995 oct 18 20 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a notes 1. the lfco output level must be measured with a load circuit of 10 k w in parallel with 15 pf. 2. the levels must be measured with load circuits, the loads depend on the type of output stage. control outputs (except href and vs); 1.2 k w at 3 v (ttl load); c l = 25 pf: data outputs (plus href and vs); 1.2 k w at 3 v (ttl load); c l =50pf. 3. other control input signals are cgce, vs, sa, hcl and hsy. 4. data output signals are yuv (15 to 0). control output signals are href, vs, hs, hsy, hcl, rtco, plin (hl), odd (vl) and gpsw0 (vblk). the effects of rise and fall times are included in the calculation of t hd;dat , t pd and t pdz . timings and levels refer to drawings and conditions illustrated in fig.10. 5. the minimum propagation delay from 3-state to data active related to falling edge of llc is 0 ns. 6. llc2 is not active while cgce = 0. 7. philips catalogue number 9922 520 30004. table 1 processing delay crystal oscillator f n nominal frequency 3rd harmonic - 26.8 - mhz d f/f n permissible frequency deviation - 50 10 - 6 - +50 10 - 6 d t/f n permissible frequency deviation with temperature - 20 10 - 6 - +20 10 - 6 c rystal specification (x1); note 7 t amb operating ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistance - 50 80 w c1 motional capacitance - 1.1 20% - ff c0 parallel capacitance - 3.5 20% - pf function typical analog delay ai21 to adcin (aout) (ns) digital delay adcin (aout) to yuvout (1/llc) (ydel = 0; cad2/3 = 1) without ampli?er or anti-alias ?lter 10 248 with ampli?er, without anti-alias ?lter 30 with ampli?er plus anti-alias ?lter (50 hz) 30 + 40 with ampli?er plus anti-alias ?lter (60 hz) 30 + 50 symbol parameter conditions min. typ. max. unit
1995 oct 18 21 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 13 timing fig.10 clock/data timing. handbook, full pagewidth t cy t cy t f t su;dat t r t llch t su;dat t hd;dat t hd;dat t hd;dat t ohd t ohd t pd t pdz t pd t ohd t ohd t llcl t llch t f t dllc2 t r clock input llc inputs control input cref outputs yuv, href, vs and hs outputs yuv (to 3-state) clock output llc output cref clock output llc2 2.4 v 1.5 v 0.6 v 2.6 v 1.5 v 0.6 v 2.6 v 1.5 v 0.6 v 2.0 v 0.8 v 2.0 v 0.8 v 2.4 v 0.6 v 2.4 v 0.6 v mgc829
1995 oct 18 22 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.11 horizontal timing. (1) see table 1. hrmv = 1 and hrfs = 0. handbook, full pagewidth 0 + 117 - 118 + 97 - 97 mgc830 cvbs hsy hcl 62 2/llc 30 2/llc y output href (50 hz) 18 2/llc 768 2/llc 176 2/llc 18 2/llc 140 2/llc 640 2/llc 64 2/llc burst plin (50 hz) processing delay cvbs -> yuv 0 + 191 - 64 0 4/llc href (60 hz) hs (60 hz) hs (50 hz) programming range (step size: 8/llc) + 127 - 128 hcl programming range (step size: 2/llc) hsy programming range (step size: 2/llc) hs (60 hz) programming range (step size: 8/llc) hs (50 hz) 94 2/llc 64 2/llc (1)
1995 oct 18 23 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.12 href timing. handbook, full pagewidth 01234 u0 v0 u1 v1 u2 end of active line start of active line 767 766 765 764 763 u766 v766 v764 u764 v762 639 638 637 636 635 u638 v638 mgc831 v636 u636 v634 one bus cycle ll27 cref href yn yn (50 hz) uvn yn (60 hz) uvn uvn href internal bus clock
1995 oct 18 24 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.13 vertical timing. (1) nominal input signal 50 hz. (2) nominal input signal 60 hz. hrmv = 1 and hrfs = 0. handbook, full pagewidth 123456789 625 input cvbs href a: 1st field (1) 2 2/llc 533 2/llc odd vs 314 315 316 317 318 319 320 321 313 input cvbs href b: 2nd field (1) 2 2/llc 61 2/llc odd vs 123456789 525 input cvbs href a: 1st field (2) 2 2/llc 441 2/llc odd vs 264 265 266 267 268 269 270 271 263 input cvbs href b: 2nd field (2) 2 2/llc 51 2/llc odd vs mgc832
1995 oct 18 25 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.14 fein timing. handbook, full pagewidth llc cref href fein yuv t su;dat t hd;dat mgc833 t ohd t pd from 3-state to 3-state table 2 digital output control oeyc fein yuv (15 : 0) 00 z 1 0 active x1 z fig.15 real time control output timing. rtco sequence is generated in llc/4. for transmission llc/2 timing is required. handbook, full pagewidth time slot: bit no.: transmitted once per line 22 1 21 19 20 15 16 17 18 7 8 9 11 10 12 13 14 sequence 19 0 67 4 3 6 4 5 2 3 0 14 45 reserved 14 fscpll-incr. mgc834 276 63 0 1 reserved 128 high low 13 hpll-incr. reserved 1 (50 hz systems) 188 (60 hz systems)
1995 oct 18 26 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 14 output formats table 3 output formats bus signal pixel byte sequence 4:1:1 format pixel byte sequence 4:2:2 format y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y7 y6 y6 y7 y6 y6 y6 y6 y6 y6 y6 y6 y6 y6 y6 y6 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y5 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y4 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y3 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y2 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 uv7 u7 u5 u3 u1 u7 u5 u3 u1 u7 v7 u7 v7 u7 v7 uv6 u6 u4 u2 u0 u6 u4 u2 u0 u6 v6 u6 v6 u6 v6 uv5 v7 v5 v3 v1 v7 v5 v3 v1 u5 v5 u5 v5 u5 v5 uv4 v6 v4 v2 v0 v6 v4 v2 v0 u4 v4 u4 v4 u4 v4 uv3 00000000u3v3u3v3u3v3 uv2 00000000u2v2u2v2u2v2 uv1 00000000u1v1u1v1u1v1 uv0 00000000u0v0u0v0u0v0 y frame 01234567 0 1 2345 uv frame 0 4 0 2 4 data rate sample frequency data rate sample frequency y llc2 llc2 llc2 llc2 u llc4 llc8 v llc4 llc8
1995 oct 18 27 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.16 yuv output signal range. ccir 601 digital levels. handbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% mgc835 a. y output range. b. u output range (b - y). c. y output range (r - y). fig.17 oscillator application. handbook, full pagewidth xtalo xtali 65 66 mgc836 xtalo l = 10 m h + /-20% c = 10 pf c = 10 pf c = 1 nf quartz (3rd harmonic) 26.8 mhz xtali 65 66 saa7110 saa7110a saa7110 saa7110a a. with quartz crystal. b. with external clock.
1995 oct 18 28 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 15 clock system 15.1 clock generation circuit the internal cgc generates the system clocks llc, llc2 and the clock reference signal cref. the internally generated lfco (triangular waveform) is multiplied by four via the analog pll (including phase detector, loop filter, vco and frequency divider). the rectangular output signals have a 50% duty factor. table 4 system clock frequencies clock frequency (mhz) 50 hz 60 hz xtal 26.8 26.8 llc 29.5 24.545454 llc2 14.75 12.272727 llc4 7.375 6.136136 llc8 3.6875 3.068181 fig.18 clock generation circuit. handbook, full pagewidth band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator delay cref mgc837 llc2 llc lfco
1995 oct 18 29 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 15.2 power-on control power-on reset is activated at power-on (using only internal cgc) and if the supply voltage falls below 3.5 v. the reset signal can be applied to reset other circuits of the digital tv system. table 5 power-on control sequence internal power-on control sequence pin output status function directly after power-on asynchronous reset y7 to y0, uv7 to uv0, rtco, plin, odd, gpsw, sda, href, hs, vs, hcl and hsy in high impedance state llc, llc2 and cref in high state direct switching to high impedance (outputs) or input mode (i/os) for 20 to 200 ms start synchronous i 2 c-bus reset sequence llc, llc2 and cref active starting i 2 c-bus reset sequence status after i 2 c-bus reset y7 to y0, uv7 to uv0, href and hs held in high impedance state vs, hcl and hsy held in input function mode sa0dh = 7dh (vtrc = 0, rtse = 1, hrmv = 1, sstb = 0, secs = 1) sa0eh = 00h (hpll = 0, oehv = 0, oeyc = 0, chrs = 0, gpsw = 0) sa31h = 00h (aos l1:0= 00, wirs = 0, wrse = 0, sqpb = 0, vblka = 0, pulio = 0) status after power-on control sequence rtco, plin, odd, gpsw and sda active after power-on (reset sequence) a complete i 2 c-bus transmission is required fig.19 power-on control circuit. handbook, full pagewidth poc v dd poc logic analog poc v dd digital mgc838 delay control clock i/o control clock output active control cgce llc reset
1995 oct 18 30 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16 i 2 c-bus description 16.1 i 2 c-bus format table 6 description of i 2 c-bus format note 1. if more than one byte data is transmitted then the auto-increment of the subaddress is performed. s slave address ack subaddress ack data (n bytes) ack p code description s start condition slave address 1001 110xb (sa = low) or 1001 111xb (sa = high) ack acknowledge generated by the slave subaddress subaddress byte, see table 7 data data byte, see table 7; note 1 p stop condition x read/write control bit: x = 0, order to write (the circuit is slave receiver) x = 1, order to read (the circuit is slave transmitter) slave address 9ch for write, 9dh for read (sa = 0) 9eh for write, 9fh for read (sa = 1 subaddress 00h to 19h decoder part 1ah to 1fh reserved 20h to 34h front-end part
1995 oct 18 31 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.2 i 2 c-bus receiver/transmitter tables table 7 ocf1 receiver slave address 10011100b, 9ch (sa = 0) and 10011110b, 9eh (sa = 1) register function sub add (1) data byte (2) d7 d6 d5 d4 d3 d2 d1 d0 dmsd-sqp + bsc slave receiver (su 00h to 19h) increment delay 00 007 idel7 006 idel6 005 idel5 004 idel4 003 idel3 002 idel2 001 idel1 000 idel0 hsy begin 50 hz 01 015 hsyb7 014 hsyb6 013 hsyb5 012 hsyb4 011 hsyb3 010 hsyb2 009 hsyb1 008 hsyb0 hsy stop 50 hz 02 023 hsys7 022 hsys6 021 hsys5 020 hsys4 019 hsys3 018 hsys2 017 hsys1 016 hsys0 hcl begin 50 hz 03 031 hclb7 030 hclb6 029 hclb5 028 hclb4 027 hclb3 026 hclb2 025 hclb1 024 hclb0 hcl stop 50 hz 04 039 hcls7 038 hcls6 037 hcls5 036 hcls4 035 hcls3 034 hcls2 033 hcls1 032 hcls0 hsy after phi1 50 hz 05 047 hphi7 046 hphi6 045 hphi5 044 hphi4 043 hphi3 042 hphi2 041 hphi1 040 hphi0 luminance control 06 055 byps 054 pref 053 bpss1 052 bpss0 051 cori1 050 cori0 049 aper1 048 aper0 hue control 07 063 huec7 062 huec6 061 huec5 060 huec4 059 huec3 058 huec2 057 huec1 056 huec0 colour killer threshold quam (pal/ntsc) 08 071 cktq4 070 cktq3 069 cktq2 068 cktq1 067 cktq0 066 xxx 065 xxx 064 xxx colour killer threshold secam 09 079 ckts4 078 ckts3 077 ckts2 076 ckts1 075 ckts0 074 xxx 073 xxx 072 xxx pal switch sensitivity 0a 087 plse7 086 plse6 085 plse5 084 plse4 083 plse3 082 plse2 081 plse1 080 plse0 secam switch sensitivity 0b 095 sese7 094 sese6 093 sese5 092 sese4 091 sese3 090 sese2 089 sese1 088 sese0 gain control chrominance 0c 103 colo 102 lfis1 101 lfis0 100 xxx 099 xxx 098 xxx 097 xxx 096 xxx standard/mode control 0d 111 vtrc 110 xxx 109 xxx 108 xxx 107 rtse 106 hrmv 105 sstb 104 secs i/o and clock control 0e 119 hpll 118 xxx 117 xxx 116 oehv 115 oeyc 114 chrs 113 xxx 112 gpsw control #1 0f 127 aufd 126 fsel 125 sxcr 124 scen 123 xxx 122 ydel2 121 ydel1 120 ydel0 control #2 10 135 xxx 134 xxx 133 xxx 132 xxx 131 xxx 130 hrfs 129 vnoi1 128 vnoi0 chrominance gain reference 11 143 chcv7 142 chcv6 141 chcv5 140 chcv4 139 chcv3 138 chcv2 137 chcv1 136 chcv0 chrominance saturation 12 151 satn7 150 satn6 149 satn5 148 satn4 147 satn3 146 satn2 145 satn1 144 satn0
1995 oct 18 32 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a luminance contrast 13 159 cont7 158 cont6 157 cont5 156 cont4 155 cont3 154 cont2 153 cont1 152 cont0 hsy begin 60 hz 14 167 hs6b7 166 hs6b6 165 hs6b5 164 hs6b4 163 hs6b3 162 hs6b2 161 hs6b1 160 hs6b0 hsy stop 60 hz 15 175 hs6s7 174 hs6s6 173 hs6s5 172 hs6s4 171 hs6b3 170 hs6s2 169 hs6s1 168 hs6s0 hcl begin 60 hz 16 183 hc6b7 182 hc6b6 181 hc6b5 180 hclb4 179 hc6b3 178 hc6b2 177 hc6b1 176 hc6b0 hcl stop 60 hz 17 191 hc6s7 190 hc6s6 189 hc6s5 188 hc6s4 187 hc6s3 186 hc6s2 185 hc6s1 184 hc6s0 hsy after phi1 60 hz 18 199 hp6i7 198 hp6i6 197 hp6i5 196 hp6i4 195 hp6i3 194 hp6i2 193 hp6i1 192 hp6i0 luminance brightness 19 207 brig7 206 brig6 205 brig5 204 brig4 203 brig3 202 brig2 201 brig1 200 brig0 duad slave receiver (su 20h to 32h) analog control #1 20 007 aind4 006 aind3 005 aind2 004 fuse1 003 fuse0 002 ains4 001 ains3 000 ains2 analog control #2 21 015 vbco 014 ms34 013 mx241 012 mx240 011 ms24 010 refs4 009 refs3 008 refs2 mixer control #1 22 023 gaco1 022 gaco0 021 csel 020 ysel 019 muyc 018 clts 017 mx341 016 mx340 clamping level control 21 23 031 cll217 030 cll216 029 cll215 028 cll214 027 cll213 026 cll212 025 cll211 024 cll210 clamping level control 22 24 039 cll227 038 cll226 037 cll225 036 cll224 035 cll223 034 cll222 033 cll221 032 cll220 clamping level control 31 25 047 cll317 046 cll316 045 cll315 044 cll314 043 cll313 042 cll312 041 cll311 040 cll310 clamping level control 32 26 055 cll327 054 cll326 053 cll325 052 cll324 051 cll323 050 cll322 049 cll321 048 cll320 gain control analog #1 27 063 hold 062 gasl 061 gai25 060 gai24 059 gai23 058 gai22 057 gai21 056 gai20 white peak control 28 071 wipe7 070 wipe6 069 wipe5 068 wipe4 067 wipe3 066 wipe2 065 wipe1 064 wipe0 sync bottom control 29 079 sbot7 078 sbot6 077 sbot5 076 sbot4 075 sbot3 074 sbot2 073 sbot1 072 sbot0 gain control analog #2 2a 087 iwip1 086 iwip0 085 gai35 084 gai34 083 gai33 082 gai32 081 gai31 080 gai30 gain control analog #3 2b 095 igai1 094 igai0 093 gai45 092 gai44 091 gai43 090 gai42 089 gai41 088 gai40 mixer control #2 2c 103 cls4 102 xxx 101 cls3 100 cls2 099 xxx 098 xxx 097 two3 096 two2 integration value gain 2d 111 ival7 110 ival6 109 ival5 108 ival4 107 ival3 106 ival2 105 ival1 104 ival0 register function sub add (1) data byte (2) d7 d6 d5 d4 d3 d2 d1 d0
1995 oct 18 33 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a notes 1. subaddresses to be reset: 0d to 7dh, 0e and 31 to 00h after reset = 0 (cgce = 0) or power-on (cgce = 1). 2. all reserved xxx-bits must be set to low, xx-bit is dont care. 3. afccs bit does not exist in saa7110a due to advanced anti-alias filter characteristic, dont care (xx). table 8 ocf1 transmitter : byte number 0 (transmitted if sstb = 0 or after reset has been 0) slave address 10011101b, 9dh (sa = 0) and 10011111b, 9fh (sa = 1 note 1. id7 to id0 indicates the version number of the ic, for example saa7110a v1 = 01h. table 9 ocf1 transmitter : byte number 1 (transmitted if sstb = 1) slave address 10011101b, 9dh (sa = 0) and 10011111b, 9fh (sa = 1) vertical blanking pulse set 2e 119 vbps7 118 vbps6 117 vbps5 116 vbps4 115 vbps3 114 vbps2 113 vbps1 112 vbps0 vertical blanking pulse reset 2f 127 vbpr7 126 vbpr6 125 vbpr5 124 vbpr4 123 vbpr3 122 vbpr2 121 vbpr1 120 vbpr0 adcs gain control 30 135 xxx 134 wisl 133 gas3 132 gad31 131 gad30 130 gas2 129 gad21 128 gad20 mixer control #3 31 143 aosl1 142 aosl0 141 wirs 140 wrse 139 sqpb 138 (3) afccs 137 vblka 136 pulio integration value white peak 32 151 wval7 150 wval6 149 wval5 148 wval4 147 wval3 146 wval2 145 wval1 144 wval0 mixer control #4 33 159 ofts 158 xxx 157 chsb 156 xxx 155 cad3 154 cad2 153 xxx 152 xxx gain update level 34 167 mud2 166 mud1 165 gudl5 164 gudl4 163 gudl3 162 gudl2 161 gudl1 160 gudl0 version status byte d7 d6 d5 d4 d3 d2 d1 d0 id7 to id0; note 1 id7 id6 id5 id4 id3 id2 id1 id0 status byte function d7 d6 d5 d4 d3 d2 d1 d0 see table 10 for explanation of bits sttc hlck fidt glim xxx wipa altd code register function sub add (1) data byte (2) d7 d6 d5 d4 d3 d2 d1 d0
1995 oct 18 34 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a table 10 explanation of bits shown in table 9 16.3 i 2 c-bus detail the i 2 c-bus receiver slave address is 9ch/9eh. dmsd-sqp slave receiver (su 00h to 19h). 16.3.1 s ubaddress 00 ( data byte 007 to 000) table 11 increment delay idel notes 1. a sign bit, designated a08 and internally set to high, indicates values are always negative. 2. the horizontal pll does not operate in this condition. the system clock frequency is set to a value fixed by the last update and is within 7.1% of the nominal frequency. bit description sttc status bit for horizontal time constant: low = tv time constant; high = vcr time constant. hlck status bit for locked horizontal frequency: low = locked; high = unlocked. fidt identi?cation bit for detected ?eld frequency: low = 50 hz; high = 60 hz. glim gain value for active luminance is limited (maximum or minimum), active high. xxx reserved wipa white peak loop is activated, active high. altd status high: line alternating colour burst has been detected (pal or secam). code status high: any colour signal has been detected. decimal multiplier delay time (step size = 4/llc) control bits (1) idel7 idel6 idel5 idel4 idel3 idel2 idel1 idel0 - 1 - 4 11111111 - 195 - 780 max. value for 60 hz 00111101 - 236 - 944 max. value for 50 hz 00010100 - 256 - 1024 outside central counter (2) 00000000
1995 oct 18 35 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.2 s ubaddress 01 ( data byte 015 to 008) table 12 horizontal synchronization begin 50 hz (hsyb) 16.3.3 s ubaddress 02 ( data byte 023 to 016) table 13 horizontal synchronization stop 50 hz (hsys) 16.3.4 s ubaddress 03 ( data byte 031 to 024) table 14 horizontal clamping begin 50 hz (hclb) 16.3.5 s ubaddress 04 ( data byte 039 to 032) table 15 horizontal clamping stop 50 hz (hcls) decimal multiplier delay time (step size = 2/llc) control bits hsyb7 hsyb6 hsyb5 hsyb4 hsyb3 hsyb2 hsyb1 hsyb0 +191 - 382 10111111 - 64 +128 11000000 decimal multiplier delay time (step size = 2/llc) control bits hsys7 hsys6 hsys5 hsys4 hsys3 hsys2 hsys1 hsys0 +191 - 382 10111111 - 64 +128 11000000 decimal multiplier delay time (step size = 2/llc) control bits hclb7 hclb6 hclb5 hclb4 hclb3 hclb2 hclb1 hclb0 +127 - 254 01111111 - 128 +256 10000000 decimal multiplier delay time (step size = 2/llc) control bits hcls7 hcls6 hcls5 hcls4 hcls3 hcls2 hcls1 hcls0 +127 - 254 01111111 - 128 +256 10000000
1995 oct 18 36 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.6 s ubaddress 05 ( data byte 047 to 040) table 16 horizontal synchronization start after phi1 50 hz (hphi) decimal multiplier delay time (step size = 8/llc) control bits hphi7 hphi6 hphi5 hphi4 hphi3 hphi2 hphi1 hphi0 +127 forbidden; outside available central counter range 01111111 +118 01110110 +117 - 32 m s (max. negative value) 01110101 - 118 +31.7 m s (max. positive value) 10001010 - 119 forbidden; outside available central counter range 10001001 - 128 10000000
1995 oct 18 37 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.7 s ubaddress 06 ( data byte 055 to 048) table 17 luminance control 16.3.8 s ubaddress 07 ( data byte 063 to 056) table 18 hue phase control huec function control bits aperture factor (aper); data bits d1 and d0 0 0 aper1 = 0; aper0 = 0 1 0.25 aper1 = 0; aper0 = 1 2 0.5 aper1 = 1; aper0 = 0 3 1.0 aper1 = 1; aper0 = 1 corner correction (cori) lsbs in 8-bit; data bits d3 and d2 0 0 (off) cori1 = 0; cori0 = 0 1 1 cori1 = 0; cori0 = 1 2 2 cori1 = 1; cori0 = 0 3 3 cori1 = 1; cori0 = 1 aperture bandpass; centre frequency (bpss); data bits d4 and d5 4.6 mhz (50 hz) 3.8 mhz (60 hz) bpss1 = 0; bpss0 = 0 4.3 mhz (50 hz) 3.4 mhz (60 hz) bpss1 = 0; bpss0 = 1 3.0 mhz (50 hz) 2.5 mhz (60 hz) bpss1 = 1; bpss0 = 0 3.2 mhz (50 hz) 2.7 mhz (60 hz) bpss1 = 1; bpss0 = 1 pre?lter active (pref); data bit d6 bypassed pref = 0 active pref = 1 chrominance trap bypass (byps); data bit d7 active cvbs mode byps = 0 bypassed s-video mode byps = 1 hue phase (degrees) control bits huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6 0 1 1 1 1 1 1 1 0 00000000 - 180 10000000
1995 oct 18 38 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.9 s ubaddress 08 c ontrol number 1( data byte 071 to 064) table 19 colour killer threshold quam (pal/ntsc) 16.3.10 s ubaddress 09 c ontrol number 2( data byte 079 to 072) table 20 colour killer threshold secam 16.3.11 s ubaddress 0a ( data byte 087 to 080) table 21 pal switch sensitivity note 1. sensitivity high means immediate sequence correction. 16.3.12 s ubaddress 0b ( data byte 095 to 088) table 22 secam switch sensitivity note 1. sensitivity high means immediate sequence correction. threshold (reference is nominal burst amplitude = 0 db) control bits cktq4 cktq3 cktq2 cktq1 cktq0 - 30 db 1 1 1 1 1 - 24 db 1 0 0 0 0 - 18 db 0 0 0 0 0 threshold (reference is nominal burst amplitude = 0 db) control bits ckts4 ckts3 ckts2 ckts1 ckts0 - 30 db 1 1 1 1 1 - 24 db 1 0 0 0 0 - 18 db 0 0 0 0 0 sensitivity control bits plse7 plse6 plse5 plse4 plse3 plse2 plse1 plse0 low 11111111 medium 1 0 000000 high (1) 00000000 sensitivity control bits sese7 sese6 sese5 sese4 sese3 sese2 sese1 sese0 low 11111111 medium 1 0 000000 high (1) 00000000
1995 oct 18 39 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.13 s ubaddress 0c ( data byte 103 to 096) table 23 gain control chrominance 16.3.14 s ubaddress 0d ( data byte 111 to 104) table 24 standard/mode control function control bits agc loop ?lter (lfis); data bits d6 and d5 slow time constant lfis1 = 0; lfis0 = 0 medium time constant lfis1 = 0; lfis0 = 1 fast time constant lfis1 = 1; lfis0 = 0 actual chrominance gain frozen lfis1 = 1; lfis0 = 1 colour on (colo); data bit d7 automatic colour killer colo = 0 colour forced on colo = 1 function control bits secam mode bit (secs); data bit d0 other standards secs = 0 secam mode secs = 1 status byte select (sstb); data bit d1 status byte = 0 (see transmitter) sstb 0 status byte = 1 (see transmitter) sstb = 1 href position select (hrmv); data bit d2 href position as saa7191 (8 llc2 later) hrmv = 0 href normal position hrmv = 1 real time outputs mode select (rtse); data bit d3 plin switched to output pin 39 odd switched to output pin 40 rtse=0 hl switched to output pin 39 vl switched to output pin 40 rtse = 1 tv/vcr mode select (vtrc); data bit d7 tv mode vtrc = 0 vtr mode vtrc = 1
1995 oct 18 40 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.15 s ubaddress 0e ( data byte 119 to 112) table 25 i/o and clock control 16.3.16 s ubaddress 0f ( data byte 127 to 120) table 26 control number 1 function control bits general purpose switch (gpsw); data bit d0 switches directly pin 64 gpsw (application dependent); vblka = 0 gpsw = 0 gpsw = 1 select chrominance input (chrs); data bit d2 controlled by byps (subaddress 06) normal position chrs = 0 digital chrominance input switched to second input channel (see fig.20) chrs = 1 output enable yuv-data (oeyc); data bit d3 yuv bus high impedance/input oeyc = 0 output yuv-bus active oeyc = 1 output enable horizontal/vertical synchronization (oehv); data bit d4 hs, href and vs high impedance/inputs oehv = 0 output hs, href and vs active oehv = 1 horizontal pll clock (hpll); data bit d7 pll closed hpll = 0 pll open, horizontal frequency ?xed hpll = 1 function control bits luminance delay compensation; steps in 2/llc (ydel); data bits d2, d1 and d0 0 steps ydel2 = 0; ydel1 = 0; ydel0 = 0 3 steps ydel2 = 0; ydel1 = 1; ydel0 = 1 - 4 steps ydel2 = 1; ydel1 = 0 ydel1 = 0 enable or disable of sync and clamp pulses; hsy and hcl (scen); data bit d4 disable sync and clamp (set to high) scen = 0 enable sync and clamp scen = 1 secam cross colour reduction (sxcr); data bit d5 reduction off sxcr = 0 reduction on sxcr = 1 field selection (fsel); data bit d6 50 hz, 625 lines fsel = 0 60 hz, 525 lines fsel = 1 automatic ?eld detection(aufd); data bit d7 field state directly controlled via fsel aufd = 0 automatic ?eld detection aufd = 1
1995 oct 18 41 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.17 s ubaddress 10 ( data byte 135 to 128) table 27 control number 2 16.3.18 s ubaddress 11 ( data byte 143 to 136) table 28 chrominance gain reference value 16.3.19 s ubaddress 12 ( data byte 150 to 144) table 29 chrominance saturation control function control bits vertical noise reduction (vnoi); data bits d1 and d0 normal mode vnoi1 = 0; vnoi0 = 0 search mode vnoi1 = 0; vnoi0 = 1 free running mode vnoi1 = 1; vnoi0 = 0 vertical noise reduction bypassed vnoi1 = 1; vnoi0 = 1 href select hrfs (hrfs); data bit d2 href matched to yuv output hrfs = 0 href matched to cvbs input hrfs = 1 reference value control bits chcv7 chcv6 chcv5 chcv4 chcv3 chcv2 chcv1 chcv0 maximum 1 1 111111 ccir-level for pal 0 1 011001 ccir-level for ntsc 0 0 101100 minimum 0 0 000000 gain control bits satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 1.999 maximum 0 1 111111 1 ccir-level 0 1 000000 0 colour off 0 0 000000 - 1 inverse chrominance 1 1 000000 - 2 inverse chrominance 1 0 000000
1995 oct 18 42 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.20 s ubaddress 13 ( data byte 158 to 152) table 30 luminance contrast control 16.3.21 s ubaddress 14 ( data byte 167 to 160) table 31 horizontal synchronization begin 60 hz (hs6b) 16.3.22 s ubaddress 15 ( data byte 175 to 168) table 32 horizontal synchronization stop 60 hz (hs6s) 16.3.23 s ubaddress 16 ( data byte 183 to 176) table 33 horizontal clamping begin 60 hz (hc6b) gain control bits cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 1.999 maximum 0 1 111111 70 ccir-level 0 1 000110 1 01000000 0 luminance off 0 0 000000 - 1 inverse luminance 1 1 000000 - 2 inverse luminance 1 0 000000 decimal multiplier delay time (step size = 2/llc) control bits hs6b7 hs6b6 hs6b5 hs6b4 hs6b3 hs6b2 hs6b1 hs6b0 +191 - 382 10111111 - 64 +128 11000000 decimal multiplier delay time (step size = 2/llc) control bits hs6s7 hs6s6 hs6s5 hs6s4 hs6s3 hs6s2 hs6s1 hs6s0 +191 - 382 10111111 - 64 +128 11000000 decimal multiplier delay time (step size = 2/llc) control bits hc6b7 hc6b6 hc6b5 hc6b4 hc6b3 hc6b2 hc6b1 hc6b0 +127 - 254 01111111 - 128 +256 10000000
1995 oct 18 43 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.3.24 s ubaddress 17 ( data byte 191 to 184) table 34 horizontal clamping stop 60 hz (hc6s) 16.3.25 s ubaddress 18 ( data byte 199 to 192) table 35 horizontal synchronization start after phi1 60 hz (hp6i) 16.3.26 s ubaddress 19 ( data byte 207 to 200) table 36 luminance brightness control decimal multiplier delay time (step size = 2/llc) control bits hc6s7 hc6s6 hc6s5 hc6s4 hc6s3 hc6s2 hc6s1 hc6s0 +127 - 254 01111111 - 128 +256 10000000 decimal multiplier delay time (step size = 8/llc) control bits hp6i7 hp6i6 hp6i5 hp6i4 hp6i3 hp6i2 hp6i1 hp6i0 +127 forbidden; outside available central counter range 01111111 +98 01100010 +97 - 32 m s (max. negative value) 01100001 - 97 +31.7 m s (max. positive value) 10011111 - 98 forbidden; outside available central counter range 10011110 - 128 10000000 offset control bits brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 255 (bright) 1 1 1 1 1 1 1 1 139 (ccir-level) 1 0 0 0 1 0 1 1 128 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0
1995 oct 18 44 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4 i 2 c-bus detail (continued) duad slave receiver (su 20h to 32h). 16.4.1 s ubaddress 20 ( data byte 007 to 000) table 37 analog control #1 function control bits analog input select 2 (ains2); data bit d0 analog input ai22 selected ains2 = 0 analog input ai21 selected ains2 = 1 analog input select 3 (ains3); data bit d1 analog input ai32 selected ains3 = 0 analog input ai31 selected ains3 = 1 analog input select 4 (ains4); data bit d2 analog input ai42 selected ains4 = 0 analog input ai41 selected aind4 = 1 analog function select (fuse); data bits d4 and d3 ampli?er plus anti-alias ?lter bypassed fuse1 = 0; fuse0 = 0 fuse1 = 0; fuse0 = 1 ampli?er active fuse1 = 1; fuse0 = 0 ampli?er plus anti-alias ?lter active fuse1 = 1; fuse0 = 1 analog input disable 2 (aind2); data bit d5 analog inputs 2 enabled aind2 = 0 analog inputs 2 disabled aind2 = 1 analog input disable 3 (aind3); data bit d6 analog inputs 3 enabled aind3 = 0 analog inputs 3 disabled aind3 = 1 analog input disable 4 (aind4); data bit d7 analog inputs 4 enabled aind4 = 0 analog inputs 4 disabled aind4 = 1
1995 oct 18 45 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.2 s ubaddress 21 ( data byte 015 to 008) table 38 analog control #2 function control bits reference select channel 2 (refs2); data bit d0 automatic clamping active refs2 = 0 reference level selected refs2 = 1 reference select channel 3 (refs3); data bit d1 automatic clamping active refs3 = 0 reference level selected refs3 = 1 reference select channel 4 (refs4); data bit d2 automatic clamping active refs4 = 0 reference level selected refs4 = 1 muxc select channel 24 (ms24); data bit d3 analog mux2 controlled by mx24 ms24 = 0 analog mux2 controlled by muxc ms24 = 1 analog mux2 control (mx24); data bits d5 and d4 adder mode mx241 = 0; mx240 = 0 channel 2 on; channel 4 off mx241 = 0; mx240 = 1 channel 2 off; channel 4 on mx241 = 1; mx240 = 0 both channels off mx241 = 1; mx240 = 1 muxc select channel 34 (ms34); data bit d6 analog mux3 controlled by mx34 ms34 = 0 analog mux3 controlled by muxc ms34 = 1 vertical blanking control off (vbco); data bit d7 vertical blanking on vbco = 0 vertical blanking off vbco = 1
1995 oct 18 46 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.3 s ubaddress 22 ( data byte 023 to 016) table 39 mixer control #1 16.4.4 s ubaddress 23 ( data byte 031 to 024) table 40 clamping level control 21 cll21 function control bits analog mux3 control (mx34); data bits d1 and d0 adder mode mx341 = 0; mx340 = 0 channel 3 on; channel 4 off mx341 = 0; mx340 = 1 channel 3 off; channel 4 on mx341 = 1; mx340 = 0 both channels off mx341 = 1; mx340 = 1 clamping function test (clts); data bit d2 normal clamping mode clts = 0 claan and claun adjusted via cll32 value for testing (do not use) clts = 1 fast digital multiplexing channel 2/3 active (muyc); data bit d3 normal mode on chr channel muyc = 0 multiplex mode on chr channel for test purposes only (do not use) muyc = 1 luminance select (ysel); data bit d4 adc 2 to cvbs ysel = 0 adc 3 to cvbs ysel = 1 chrominance select (csel); data bit d5 adc 3 to chr (muxc not inverse; muyc = 1) csel = 0 adc 2 to chr (muxc inverse; muyc = 1) csel = 1 automatic gain control (gaco); data bits d7 and d6 automatic gain control off gaco1 = 0; gaco0 = 0 automatic gain control channel 2 gaco1 = 0; gaco0 = 1 automatic gain control channel 3 gaco1 = 1; gaco0 = 0 automatic gain control channel 4 gaco1 = 1; gaco0 = 1 decimal clamp level control bits cll217 cll216 cll215 cll214 cll213 cll212 cll211 cll210 1 00000001 64 01000000 128 10000000 254 11111110
1995 oct 18 47 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.5 s ubaddress 24 ( data byte 039 to 032) table 41 clamping level control 22 cll22 16.4.6 s ubaddress 25 ( data byte 047 to 040) table 42 clamping level control 31 cll31 16.4.7 s ubaddress 26 ( data byte 055 to 048) table 43 clamping level control 32 cll32 decimal clamp level control bits cll227 cll226 cll225 cll224 cll223 cll222 cll221 cll220 1 00000001 64 01000000 128 10000000 254 11111110 decimal clamp level control bits cll317 cll316 cll315 cll314 cll313 cll312 cll311 cll310 1 00000001 64 01000000 128 10000000 254 11111110 decimal clamp level control bits cll327 cll326 cll325 cll324 cll323 cll322 cll321 cll320 1 00000001 64 01000000 128 10000000 254 11111110
1995 oct 18 48 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.8 s ubaddress 27 ( data byte 063 to 056); gain control analog #1 table 44 static gain control channel 2 (gai2); data bits d5 to d0 table 45 gain mode select (gasl); data bit d6 table 46 automatic control integration (hold); data bit d7 16.4.9 s ubaddress 28 ( data byte 071 to 064) table 47 white peak control wipe 16.4.10 s ubaddress 29 ( data byte 079 to 072) table 48 sync bottom control sbot decimal multiplier gain (step size = 0.19 db) control bits gai25 gai24 gai23 gai22 gai21 gai20 0 - 2.82 db 000000 15 0db 001111 31 3db 011111 47 6db 101111 63 9db 111111 function control bit gasl difference value integration 0 fix value integration 1 function control bit hold agc active 0 agc integration hold (freeze) 1 decimal white peak level control bits wipe7 wipe6 wipe5 wipe4 wipe3 wipe2 wipe1 wipe0 128 10000000 254 11111110 255 (white peak control off) 1 1 1 1 1 1 1 1 decimal sync bottom level control bits sbot7 sbot6 sbot5 sbot4 sbot3 sbot2 sbot1 sbot0 1 00000001 254 11111110
1995 oct 18 49 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.11 s ubaddress 2a ( data byte 087 to 080); gain control analog #2 table 49 static gain control channel 3 (gai3); data bits d5 to d0 table 50 integration factor white peak (iwip); data bits d7 and d6 16.4.12 s ubaddress 2b ( data byte 095 to 088); gain control analog #3 table 51 static gain control channel 4 (gai4); data bits d5 to d0 table 52 integration factor normal gain (igai); data bits d7 and d6 decimal multiplier gain (step size = 0.19 db) control bits gai35 gai34 gai33 gai32 gai31 gai30 0 - 2.82 db 0 0 0 0 0 0 15 0db 001111 31 3db 011111 47 6db 101111 63 9db 111111 function control bits fast selection iwip1 = 0; iwip0 = 0 | iwip1 = 0; iwip0 = 1 | iwip1 = 1; iwip0 = 0 slow selection iwip1 = 1; iwip0 = 1 decimal multiplier gain (step size = 0.19 db) control bits gai45 gai44 gai43 gai42 gai41 gai40 0 - 2.82 db 0 0 0 0 0 0 15 0db 001111 31 3db 011111 47 6db 101111 63 9db 111111 function control bits slow selection igai1 = 0; igai0 = 0 | igai1 = 0; igai0 = 1 | igai1 = 1; igai0 = 0 fast selection igai1 = 1; igai0 = 1
1995 oct 18 50 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.13 s ubaddress 2c ( data byte 103 to 096) table 53 mixer control #2 16.4.14 s ubaddress 2d ( data byte 111 to 104) table 54 integration value gain (ival) 16.4.15 s ubaddress 2e ( data byte 119 to 112) table 55 blanking pulse vblk-set (vbps) notes 1. maximum for 60 hz. 2. maximum for 50 hz. function control bits twos complement channel 2 (two2); data bit d0 unipolar two2 = 0 twos complement (normal mode) two2 = 1 twos complement channel 3 (two3); data bit d1 unipolar two3 = 0 twos complement (normal mode) two3 = 1 clamping level select channel 2 (cls2); data bit d4 cll21 active cls2 = 0 cll22 active cls2 = 1 clamping level select channel 3 (cls3); data bit d5 cll31 active cls3 = 0 cll32 active cls3 = 1 clamping level select channel 4 (cls4); data bit d7 cll2n active cls4 = 0 cll3n active cls4 = 1 decimal integration value gain control bits ival7 ival6 ival5 ival4 ival3 ival2 ival1 ival0 1 00000001 255 11111111 decimal multiplier set line number (step size = 2) control bits vbps7 vbps6 vbps5 vbps4 vbps3 vbps2 vbps1 vbps0 0 0 after rising edge of vs 0 0000000 131 (1) 262 after rising edge of vs 1 0000011 156 (2) 312 after rising edge of vs 1 0011100
1995 oct 18 51 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.16 s ubaddress 2f ( data byte 127 to 120) table 56 blanking pulse vblk-reset (vbpr) notes 1. maximum for 60 hz. 2. maximum for 50 hz. 16.4.17 s ubaddress 30 ( data byte 135 to 128) table 57 adcs gain control decimal multiplier reset line number (step size = 2) control bits vbpr7 vbpr6 vbpr5 vbpr4 vbpr3 vbpr2 vbpr1 vbpr0 0 0 after rising edge of vs 0 0 0 0 0 0 0 0 131 (1) 262 after rising edge of vs 1 0 0 0 0 0 1 1 156 (2) 312 after rising edge of vs 1 0 0 1 1 1 0 0 function control bits fix gain adc channel 2 (gad2); data bits d1 and d0 0 db gad21 = 0; gad20 = 0 0.05 db gad21 = 0; gad20 = 1 0.10 db gad21 = 1; gad20 = 0 0.15 db gad21 = 1; gad20 = 1 gain adc select channel 2 (gas2); data bit d2 fix gain via i 2 c-bus gad2 gas2 = 0 automatic gain via loop gas2 = 1 fix gain adc channel 3 (gad3); data bits d4 and d3 0 db gad31 = 0; gad30 = 0 0.05 db gad31 = 0; gad30 = 1 0.10 db gad31 = 1; gad30 = 0 0.15 db gad31 = 1; gad30 = 1 gain adc select channel 3 (gas3); data bit d5 fix gain via i 2 c-bus gad3 gas3 = 0 automatic gain via loop gas3 = 1 white peak mode select (wisl); data bit d6 difference value integration wisl = 0 fix value integration wisl = 1
1995 oct 18 52 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.18 s ubaddress 31 ( data byte 143 to 136) table 58 mixer control #3 16.4.19 s ubaddress 32 ( data byte 151 to 144) table 59 integration value white peak (wval) function control bits pulses i/o control (pulio); data bit d0 hcl and hsy to input pins pulio = 0 hcl and hsy to output pins pulio = 1 pin function switch (vblka); data bit d1 gpsw active (normal) vblka = 0 vblk test output active vblka = 1 dmsd-sqp bypassed (sqpb); data bit d3 dmsd data to yuv output sqpb = 0 a/d data to yuv output for test purposes only (do not use) sqpb = 1 white peak slow up integration enable (wrse); data bit d4 hold in white peak mode wrse = 0 slow up integration with 1 value in h or v (dependent on wirs) wrse = 1 white peak slow up integration select (wirs); data bit d5 slow up integration with 1 value per line wris = 0 slow up integration with 1 value per ?eld wris = 1 analog test select (aosl); data bits d7 and d6 aout connected to ground aosl1 = 0; aosl0 = 0 aout connected to input ad2 aosl1 = 0; aosl0 = 0 aout connected to input ad3 aosl1 = 1; aosl0 = 1 aout connected to channel 4 aosl1 = 1; aosl0 = 1 decimal integration value white peak control bits wval7 wval6 wval5 wval4 wval3 wval2 wval1 wval0 1 00000001 127 (max.) 01111111
1995 oct 18 53 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 16.4.20 s ubaddress 33 ( data byte 159 to 152) table 60 mixer control #4 16.4.21 s ubaddress 34 ( data byte 167 to 160) table 61 gain update level (gudl; data bits d5 to d0 table 62 muxc phase delay (mud2); data bits d7 and d6 function control bits clock select ad2 (cad2); data bit d2 llc for test purposes only (do not use) cad2 = 0 llc/2 cad2 = 1 clock select ad3 (cad3); data bit d3 llc for test purposes only (do not use) cad3 = 0 llc/2 cad3 = 1 change sign bit uv data (chsb); data bit d5 uv output unipolar chsb = 0 uv output twos complement chsb = 1 output format select (ofts); data bit d7 4 : 1 : 1 format ofts = 0 4 : 2 : 2 format ofts = 1 decimal hysteresis for 8-bit gain update new gain - old gain control bits gudl5 gudl4 gudl3 gudl2 gudl1 gudl0 0 0lsb >0 000000 7 7lsb >7 000111 >31 off always 1 xxxxx function control bit mud no phase delay mud2 = 0; mud1 = 0 1 llc cycle phase delay for claa path mud2 = 0; mud1 = 1 2 llc cycle phase delay for claa path mud2 = 1; mud1 = 0 3 llc cycle phase delay for claa path mud2 = 1; mud1 = 1
1995 oct 18 54 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 17 source selection management table 63 source selection management examples input example 1 example 2 example 3 example 4 signal mode signal mode signal mode signal mode ain21 cvbs1 0 cvbs1 0 y1 6 y1 6 ain22 cvbs2 1 c2 7 c2 7 cvbs2 1 ain31 cvbs3 2 y2 7 y2 7 cvbs3 2 ain32 cvbs4 3 c3 8 c3 8 cvbs4 3 ain41 cvbs5 4 y3 8 y3 8 cvbs5 4 ain42 cvbs6 5 cvbs6 5 c1 6 c1 6 l l pagewidth gain4 aaf4 gain3 aaf3 gain2 aaf2 adc3 adc2 ains4 csel chrs v byps cll32 cll31 cll22 cll21 chroma luma ysel ains3 cls4 aind4 aind3 aind2 ains2 clamp con3 clamp con2 gain con gai4 clamp up/down clamp up/down gai3 gai2 ref128 refs2 refs3 refs4 ai22 ai21 ai32 ai31 ai42 ai41 clamp clamp clamp gaco mx340 mx341 mx240 mx241 cls3 cls2 mgc839 fig.20 source selection overview. all switch control bits set to low. fig.21 mode 0; cvbs1. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc840 chroma luma ad3 ad2
1995 oct 18 55 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.22 mode 1; cvbs2. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc841 chroma luma ad3 ad2 fig.23 mode 2; cvbs3. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc842 chroma luma ad3 ad2 fig.24 mode 3; cvbs4. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc843 chroma luma ad3 ad2 fig.25 mode 4; cvbs5. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc844 chroma luma ad3 ad2
1995 oct 18 56 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.26 mode 5; cvbs6. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc845 chroma luma ad3 ad2 fig.27 mode 6; y1 + c1. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc846 chroma luma ad3 ad2 fig.28 mode 7; y2 + c2. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc847 chroma luma ad3 ad2 fig.29 mode 8; y3 + c3. handbook, full pagewidth ai41 ai42 ai31 ai32 ai21 ai22 mgc848 chroma luma ad3 ad2
1995 oct 18 57 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a table 64 i 2 c-bus control control input (1) mode 01234 5 6 7 89 subaddress 20 aind4 1 1 1 1 0 0 0 1 0 - aind3 1 1 0 0 1 1 1 0 0 - aind2 0 0 1 1 1 1 0 0 1 - fuse1 1 ---- - - - -- fuse0 1 ---- - - - -- ains4 x x x x 1 0 0 x 1 - ains3 x x 1 0 x x 0 1 0 - ains2 1 0 x x x x 1 0 x - subaddress 21 vbco 0 ---- - - - -- ms34 0 ---- - - - -- mx241 0 0 x x x x 0 0 1 - mx240 0 0 x x x x 0 0 1 - ms24 0 ---- - - - -- refs4 1 1 1 1 0 0 0 1 0 - refs3 1 1 0 0 1 1 1 0 0 - refs2 0 0 1 1 1 1 0 0 1 - subaddress 22 gaco1 0 0 1 1 1 1 0 1 1 - gaco0 1 1 0 0 1 1 1 0 1 - csel x x x x x x 0 1 0 - ysel 0 0 1 1 1 1 0 1 0 - muyc 0 ---- - - - - 0 clts 0 ---- - - - - 0 mx341 x x 0 0 1 1 1 0 0 - mx340 x x 1 1 0 0 0 1 1 - subaddress 2c cls4 x x x x 1 1 1 x 0 - gabl 0 ---- - - - -- cls3 x x 0 0 0 0 1 0 1 - cls2 0 0 x x x x 0 1 x - 4lsb 0011 ---- - - - - 0011 byps 0 0 0 0 0 0 1 1 1 - subaddresses su 20h d9h d8h bah b8h 7ch 78h 59h 9ah 3ch - 21h 16h 16h 05h 05h 03h 03h 12h 14h 21h -
1995 oct 18 58 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a notes 1. cll21 = 65d, cll22 = 128d, cll31 = 65d, cll32 = 128d, gai4 = 15d, gai3 = 15dgai2 = 15d; x set 0. 2. optional: values for ad gain (+2 lsbs gain resolution) active [not active: for all modes 40h]. 18 anti-alias filter graphs 22h 40h 40h 91h 91h d2h d2h 42h b1h c1h - 2ch 03h 03h 03h 03h 83h 83h a3h 13h 23h - 06h 0xxxxxxx 1xxxxxxx - 30h (2) 44h 44h 60h 60h 60h 60h 44h 60h 44h - control input (1) mode 01234 5 6 7 89 fig.30 anti-alias filter graph for saa7110a . (1) 50 hz. (2) 60 hz. handbook, full pagewidth + 3 - 39 0 2 4 6 8 10 12 14 16 f (mhz) mgc849 - 3 - 9 - 15 - 21 - 27 - 33 (1) (2) a (db)
1995 oct 18 59 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.31 anti-alias filter graph for saa7110 . (1) 50 hz, afccs = 0, llc = 29.50 mhz. (2) 50 hz, afccs = 1, llc = 29.50 mhz. (3) 60 hz, afccs = 0, llc = 24.54 mhz. (3) 60 hz, afccs = 1, llc = 24.54 mhz. handbook, full pagewidth + 3 - 39 0 5 10 15 20 25 30 f (mhz) mgc850 - 3 - 9 - 15 - 21 - 27 - 33 (4) (1) (3) (2) a (db) 19 coring function 19.1 coring function adjustment by subaddress 06h to affect band ?lter output adjustment the thresholds are related to the 13-bit word width in the luminance processing part and influence the 1 to 3 lsb (yo to y2) with respect to the 8-bit luminance output. table 65 cori control settings a, b and c of fig.32 control bits cori1 cori0 a0 1 b1 0 c1 1 fig.32 coring function. handbook, halfpage - 64 - 32 0 + 64 + 64 + 32 - 32 - 64 0 mgc851 + 32 a b c c b a
1995 oct 18 60 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 20 luminance filter graphs fig.33 luminance control: su06h, 50 hz/cvbs mode, prefilter on and coring off (40 to 63h). handbook, full pagewidth 8 f y (mhz) 18 - 30 02 46 mgc852 6 vy (db) - 18 - 6 63h 73h 53h 43h 40h 43h 53h 73h 63h 40h fig.34 luminance control: su06h, 50 hz/cvbs mode, prefilter on and coring off (40 to 43h). handbook, full pagewidth 8 f y (mhz) 18 - 30 02 46 mgc853 6 vy (db) - 18 - 6 43h 42h 41h 40h 43h 42h 41h 40h
1995 oct 18 61 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.35 luminance control: su06h, 50 hz/cvbs mode, prefilter off and coring off. handbook, full pagewidth 8 f y (mhz) 18 - 30 02 46 mgc854 6 vy (db) - 18 - 6 23h 33h 13h 03h 00h 03h 13h 33h 23h 00h fig.36 luminance control: su06h, 50 hz/y + c mode, prefilter off and coring off. handbook, full pagewidth 8 18 - 30 02 46 mgc855 6 vy (db) - 18 - 6 83h 82h 81h 80h f y (mhz)
1995 oct 18 62 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.37 luminance control: su06h, 50 hz/y + c mode, prefilter on and coring off. handbook, full pagewidth 8 18 - 30 02 46 mgc856 6 vy (db) - 18 - 6 c3h c2h c1h c0h f y (mhz) fig.38 luminance control: su06h, 60 hz/cvbs mode, prefilter on and coring off. handbook, full pagewidth f y (mhz) 18 - 30 0246 mgc857 6 vy (db) - 18 - 6 63h 73h 53h 43h 40h 43h 53h 73h 63h 40h
1995 oct 18 63 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.39 luminance control: su06h, 60 hz/cvbs mode, prefilter on and coring off. handbook, full pagewidth f y (mhz) 18 - 30 0246 mgc858 6 vy (db) - 18 - 6 43h 42h 41h 40h 43h 42h 41h 40h fig.40 luminance control: su06h, 60 hz/cvbs mode, prefilter off and coring off. handbook, full pagewidth f y (mhz) 18 - 30 0246 mgc859 6 vy (db) - 18 - 6 23h 33h 13h 03h 00h 03h 13h 33h 23h 00h
1995 oct 18 64 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a fig.41 luminance control: su06h, 60 hz/y + c mode, prefilter off and coring off. handbook, full pagewidth 8 18 - 30 02 46 mgc860 6 vy (db) - 18 - 6 83h 82h 81h 80h f y (mhz) fig.42 luminance control: su06h, 60 hz/y + c mode, prefilter on and coring off. handbook, full pagewidth 8 f y (mhz) 18 - 30 02 46 mgc861 6 vy (db) - 18 - 6 c3h c2h c1h c0h
1995 oct 18 65 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 21 i 2 c-bus start set-up the values shown in table 66 are optimized for the ebu colour bar (100% white and 75% chrominance amplitude) signal. the decoder output signal level fulfils the ccir 601 specification. the input of 100% colour bar level is possible, but the signal (white) peak function reduces the digital luminance output. with a different set-up it is possible to proceed 100% colour bar signal without luminance colour bar reduction. the method is to modify the ad input range for this input level by reducing the gain reference value (sbot > 06h) and adjusting the digital y output level with contrast and brightness control. table 66 i 2 c-bus start set-up su name function binary hex 76543210 start 00 idel7 to idel0 increment delay 01001100 4c 01 hsyb7 to hsyb0 horizontal sync (hsy) begin 50 hz 00111100 3c 02 hsys7 to hsys0 horizontal sync (hsy) stop 50 hz 00001101 0d 03 hclb7 to hclb0 horizontal clamp (hcl) begin 50 hz 11101111 ef 04 hcls7 to hcls0 horizontal clamp (hcl) stop 50 hz 10111101 bd 05 hphi7 to hphi0 horizontal sync after phi1 50 hz 11110000 f0 06 byps, pref, bpss1 to bpss0, cori1 to cori0, aper1 to aper0 luminance control 00000000 00 07 huec7 to huec0 hue control 00000000 00 08 cktq4 to cktq0, xxx colour killer threshold pal 11111xxx f8 09 ckts4 to ckts0, xxx colour killer threshold secam 11111xxx f8 0a plse7 to plse0 pal switch sensitivity 01100000 60 0b sese7 to sese0 secam switch sensitivity 01100000 5b 0c colo, lfis1 to lfis0, xxxxx gain control chrominance 0 0 0xxxxx 00 0d vtrc, xxx, rtse, hrmv, sstb, secs standard/mode control 0 x x x 0110 06 0e hpll, xx, oehv, oeyc, chrs, x, gpsw i/o and clock control 0 x x 1 1 0 x 0 18 0f aufd, fsel, sxcr, scen, x, ydel2 to ydel0 control #1 1001x000 90 10 xxxxx, hrfs, vnoi1 to vnoi0 control #2 xxxxx0 0 0 00 11 chcv7 to chcv0 pal chrominance gain reference 01011001 59 chcv7 to chcv0 ntsc 00101100 2c 12 satn7 to satn0 chrominance saturation 01000000 40 13 cont7 to cont0 luminance contrast 01000110 46 14 hs6b7 to hs6b70 horizontal sync (hsy) begin 60 hz 01000010 42 15 hs6s7 to hs6s0 horizontal sync (hsy) stop 60 hz 00011010 1a 16 hc6b7 to hc6b0 horizontal clamp (hcl) begin 60 hz 11111111 ff 17 hc6s7 to hc6s0 horizontal clamp (hcl) stop 60 hz 11011010 da 18 hp6i7 to hp6i0 horizontal sync after phi1 60 hz 11110000 f0 19 brigi7 to brig0 luminance brightness 10001011 8b
1995 oct 18 66 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 21.1 remarks to table 66 values recommended for a cvbs (pal or ntsc) signal, input ai21 via a/d channel 2 (mode 0), and 4 : 2 : 2 ccir output signal level; all x values must be set low, x* value is dont care; hphi and hp6i are application dependent. 1a-1f reserved 20 aind4, aind3, aind2, fuse1 to fuse0, ains4, ains3, ains2 analog control #1 11011001 d9 21 vbco, ms34, mx241 to mx240, ms24, refs4, refs3, refs2 analog control #2 00010110 16 22 gaco1 to gaco0, csel, ysel, muyc, clts, mx341 to mx340 mixer control #1 01000000 40 23 cll217 to cll210 clamping level control channel 21 01000001 41 24 cll227 to cll220 clamping level control channel 22 10000000 80 25 cll317 to cll310 clamping level control channel 31 01000001 41 26 cll327 to cll320 clamping level control channel 32 10000000 80 27 hold, gasl, gai25 to gai20 gain control analog #1 01001111 4f 28 wipe7 to wipe0 white peak control 11111110 fe 29 sbot7 to sbot0 sync bottom control 00000001 01 2a iwip1 to iwip0, gai35 to gai30 gain control analog #2 11001111 cf 2b igai1 to igai0, gai45 to gai40 gain control analog #3 00001111 0f 2c cls4, x, cls3, cls2, two3, two2 mixer control #2 0 x 0 0 x x 1 1 03 2d ival7 to ival0 integration value gain 00000001 01 2e vbps7 to vbps0; 50 hz vertical blanking pulse set 10011010 9a vbps7 to vbps0; 60 hz 10000001 81 2f vbpr7 to vbpr0; 50 hz vertical blanking pulse reset 00000011 03 vbpr7 to vbpr0; 60 hz 00000011 30 x, wisl, gas3, gad31 to gad30, gas2, gad21 to gad20 adcs gain control x 1000000 44 31 aosl1 to aosl0, wirs, wrse, sqpb, x, vblka, pulio mixer control #3 01110x*01 71 32 wval7 to wval0 integration value white peak 00000010 02 33 ofts, x, chsb, x, cad3, cad2, xx mixer control #4 1 x 0 x 1 1 x x 8c 34 mud2, mud1, gudl5 to gudl0 gain update level 00000011 03 su name function binary hex 76543210 start
1995 oct 18 67 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 22 application information handbook, full pagewidth q1(26.8 mhz) y7 to y0 scl v dd ai32 fein (muxc) sda cgce aout rtco vs llc odd (vl) plin (hl) gpsw (vblk) lfco reset cref llc2 href v ss v ssa v dda v ssa v dd v ss v dd1 v dd2 v dd3 v dd4 v dd5 v ss hs y7 y6 y5 y4 y3 y2 y1 y0 v ss saa7110 saa7110a r4 75 w c24 10 nf c7 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf c8 c9 c11 c12 c13 c14 c15 r7 1 k w c17 l1 10 m h c16 1 nf 10 pf 10 pf c18 r8 1 k w 27 34 44 52 68 16 12 20 24 45 46 47 48 49 50 53 54 42 41 3 23 29 40 64 39 30 31 32 26 hsy hcl 36 37 38 9 8 7 421 28 35 43 51 67 14 10 18 25 22 15 6 5 63 33 66 65 i.c. i.c. mgc862 v ssa i.c. 100 nf 100 nf 100 nf c10 ai31 r3 75 w c3 10 nf 17 v ssa ai42 r6 75 w c6 10 nf 11 v ssa ai41 r5 75 w c5 10 nf 13 v ssa ai22 r2 75 w c2 10 nf 19 v ssa v ss ai21 r1 75 w c1 10 nf 21 v ssa uv7 to uv0 uv7 uv6 uv5 uv4 uv3 uv2 uv1 uv0 55 56 57 58 59 60 61 62 xtalo xtali sa ap sp fig.43 application diagram. unused analog inputs should not be connected.
1995 oct 18 68 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth 18 25 63 33 65 66 14 22 10 67 51 43 35 28 4 2 1789 40 30 29 31 32 26 36 37 reset lfco cref llc2 llc n.c. i.c. i.c. i.c. hcl hsy reset cref lfco2 lfco resn cref llca odd (vl) v ssa0 v ssa v ss v ssa2 v ssa3 v ssa4 v dda v ddd v ss(s) v ss v ss v ss v ss v ss v ss v ssa p ord v ssd v ss sa ap sp fein (muxc) 1 k w 1 k w r7 cgce xtalo l1 c16 c17 c18 xtali (26.8 mhz) q1 1 nf 10 m h 10 pf 10 pf 19 8,17 5 11 12 15 7 34 6, 9 13, 18 10 20 14 llc2b c20 0.1 m f llc2a llcb ms 1 2 16 ce r10 c21 c22 100 nf 100 nf saa7197 lfcosel mgc863 saa7110 saa7110a fig.44 application diagram with external clock generator circuit (cgc). the ocf1 supports for special applications the use of an external cgc (saa7197). for normal operation the built-in cgc fulfils all requirements.
1995 oct 18 69 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 23 start-up, source select and standard detection flow example fig.45 software flow example. handbook, full pagewidth power on mode 0 set-up initialization start source select refs active mode select refs off clamp active pal set-up ntsc set-up b&w50 set-up b&w60 set-up stop secam set-up standard automatic ?status byte? precharge clamping capacitor mode 0 to 7 b&w50? yes = xx0xxx00 b&w60? yes = xx1xxx00 ntsc? yes = xx1xxxxx secam? yes = xx0xxx01 b&w50? b&w60? ntsc? no no no secam? no yes yes yes yes without standard routine mgc864
1995 oct 18 70 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 23.1 code 0 startup and standard procedure slave 9c !ocf1 ntsc-setup sub 00 write 4c 3c 0d ef bd f0 00 00 f8 f8 60 60 00 06 18 90 00 2c 40 46 42 1a ff da f0 8b 00 00 00 00 00 00 d9 17 40 41 80 41 80 4f fe 01 cf 0f 03 01 81 03 44 75 01 8c 03 sub 21 write 16 !refs off clamp aktiv read 1 !status? #standard if 1 @xx0xxx00 !no color then goto bw_50hz endif if 1 @xx1xxx00 !no color then goto bw_60hz endif sub 06 write 00 endif if 1 @xx1xxxxx !60hz then goto ntsc endif if 1 @xx0xxxxx !50hz then goto pal endif #bw_50hz print "black&white" sub 06 write 80 sub 2e write 9a !vbps goto stop #bw_60hz print "black&white" sub 06 write 80 sub 2e write 81 !vbps goto stop #ntsc sub 0d write 06 !secs -> 0 sub 11 write 2c !chcv sub 2e write 81 !vbps print "ntsc" goto stop #pal sub 0d write 06 !secs -> 0 sub 11 write 59 !chcv sub 2e write 9a !vbps pause %150 !150ms if 1 @xx0xxx01 then goto secam else print "pal" goto stop #secam sub 0d write 07 !secs -> 1 print "secam" goto stop #stop 23.2 mode 0 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 0 sub 20 write d9 !ai21 active sub 21 write 17 !refs on sub 22 write 40 !ad2->luma and chroma sub 2c write 03 !clamp select sub 30 write 44 !gain ad2 active sub 31 write 75 !aosl -> 01b sub 21 write 16 !refs off clamp aktiv 23.3 mode 1 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 1 sub 20 write d8 !ai22 active sub 21 write 17 !refs on sub 22 write 40 !ad2->luma and chroma sub 2c write 03 !clamp select sub 30 write 44 !gain ad2 active sub 31 write 75 !aosl -> 01b sub 21 write 16 !refs off clamp aktiv 23.4 mode 2 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 2 sub 20 write ba !ai31 active sub 21 write 07 !refs on sub 22 write 91 !ad3->luma and chroma sub 2c write 03 !clamp select sub 30 write 60 !gain ad3 active sub 31 write b5 !aosl -> 10b sub 21 write 05 !refs off clamp aktiv 23.5 mode 3 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 3 sub 20 write b8 !ai32 active sub 21 write 07 !refs on sub 22 write 91 !ad3->luma and chroma sub 2c write 03 !clamp select sub 30 write 60 !gain ad3 active sub 31 write b5 !aosl -> 10b sub 21 write 05 !refs off clamp aktiv
1995 oct 18 71 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 23.6 mode 4 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 4 sub 20 write 7c !ai41 active sub 21 write 07 !refs on sub 22 write d2 !ad3->luma and chroma sub 2c write 83 !clamp select sub 30 write 60 !gain ad3 active sub 31 write b5 !aosl -> 10b sub 21 write 03 !refs off clamp aktiv 23.7 mode 5 source select procedure slave 9c !ocf1 sub 06 write 00 !cvbs mode 5 sub 20 write 78 !ai41 active sub 21 write 07 !refs on sub 22 write d2 !ad3->luma and chroma sub 2c write 83 !clamp select sub 30 write 60 !gain ad3 active sub 31 write b5 !aosl -> 10b sub 21 write 03 !refs off clamp aktiv 23.8 mode 6 source select procedure slave 9c !ocf1 sub 06 write 80 !y+c mode 6 sub 20 write 59 !ai21=y, ai42=c sub 21 write 17 !refs on sub 22 write 42 !ad2->luma, ad3->chr sub 2c write a3 !clamp select sub 30 write 44 !gain ad2 active sub 31 write 75 !aosl -> 01 sub 21 write 12 !refs off clamp aktiv 23.9 mode 7 source select procedure slave 9c !ocf1 sub 06 write 80 !y+c mode 7 sub 20 write 9a !ai31=y, ai22=c sub 21 write 17 !refs on sub 22 write b1 !ad3->luma, ad2->chr sub 2c write 13 !clamp select sub 30 write 60 !gain ad3 active sub 31 write b5 !aosl -> 10b sub 21 write 14 !refs off clamp aktiv 23.10 mode 8 source select procedure slave 9c !ocf1 sub 06 write 80 !y+c mode 8 sub 20 write 3c !ai41=y, ai32=c sub 21 write 27 !refs on sub 22 write c1 !ad2->luma, ad3->chr sub 2c write 23 !clamp select sub 30 write 44 !gain ad2 active sub 31 write 75 !aosl -> 01 sub 21 write 21 !refs off clamp aktiv
1995 oct 18 72 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 24 package outline references outline version european projection issue date iec jedec eiaj note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot188-2 44 60 68 1 9 10 26 43 27 61 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 92-11-17 95-03-11 plcc68: plastic leaded chip carrier; 68 leads sot188-2 unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b mm 4.57 4.19 0.51 3.30 0.53 0.33 0.021 0.013 1.27 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) d (1) 24.33 24.13 h d 25.27 25.02 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.13 a 3 0.25 0.01 0.05 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.958 0.950 24.33 24.13 0.958 0.950 0.995 0.985 25.27 25.02 0.995 0.985 e e e d 23.62 22.61 0.930 0.890 23.62 22.61 0.930 0.890 0.085 0.032 0.026 0.048 0.042 e e inches d e
1995 oct 18 73 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 25 soldering 25.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 25.2 re?ow soldering reflow soldering techniques are suitable for all plcc packages. the choice of heating method may be influenced by larger plcc packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 25.3 wave soldering wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 25.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1995 oct 18 74 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a 26 definitions 27 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 28 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1995 oct 18 75 philips semiconductors product speci?cation one chip front-end 1 (ocf1) saa7110; saa7110a notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40-2783749, fax. (31)40-2788399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852)2319 7888, fax. (852)2319 7700 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358)0-615 800, fax. (358)0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040)2783749, fax. (040)2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scd44 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 483061/1500/01/pp76 date of release: 1995 oct 18 document order number: 9397 750 00368

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